LOCK=UNLOCKED, EMIFCS1EN=DISABLED, ETMEN=DISABLED, JTAGEN=DISABLED, MATMD=PINMATCH, EMIFWIDTH=AWIDTH_8, EMIFBE0BEN=DISABLED, EVREGRMD=RESET_ON_ANY, EMIFEN=DISABLED
Global Port Control 1
| JTAGEN | JTAG Enable. 0 (DISABLED): JTAG functionality is not pinned out. 1 (ENABLED): JTAG functionality is pinned out. |
| ETMEN | ETM Enable. 0 (DISABLED): ETM not pinned out. 1 (ENABLED): ETM is enabled and pinned out. |
| EMIFBE0BEN | EMIF 0 (DISABLED): Disable the EMIF /BE0 pin. 1 (ENABLED): Enable the /BE0 pin if EMIFEN is also set to 1. |
| EMIFCS1EN | EMIF CS1 Pin Enable. 0 (DISABLED): Disable the EMIF CS1 pin. 1 (ENABLED): Enable the CS1 pin if EMIFEN is also set to 1. |
| EMIFEN | EMIF Enable. 0 (DISABLED): Disable the EMIF pins. 1 (ENABLED): EMIF is enabled and pinned out. |
| EMIFWIDTH | EMIF Width. 0 (AWIDTH_8): EMIF Address[7:0] 1 (AWIDTH_9): EMIF Address[8:0], PB2.8 = A[8] 2 (AWIDTH_10): EMIF Address[9:0], PB2.7 = A[9] 3 (AWIDTH_11): EMIF Address[10:0], PB2.6 = A[10] 4 (AWIDTH_12): EMIF Address[11:0], PB2.5 = A[11] 5 (AWIDTH_13): EMIF Address[12:0], PB2.4 = A[12] 6 (AWIDTH_14): EMIF Address[13:0], PB2.3 = A[13] 7 (AWIDTH_15): EMIF Address[14:0], PB2.2 = A[14] 8 (AWIDTH_16): EMIF Address[15:0], PB2.1 = A[15] 9 (AWIDTH_17): EMIF Address[16:0], PB2.0 = A[16] 10 (AWIDTH_18): EMIF Address[17:0], PB1.15 = A[17] 11 (AWIDTH_19): EMIF Address[18:0], PB1.14 = A[18] 12 (AWIDTH_20): EMIF Address[19:0], PB1.13 = A[19] 13 (AWIDTH_21): EMIF Address[20:0], PB1.12 = A[20] 14 (AWIDTH_22): EMIF Address[21:0], PB1.11 = A[21] 15 (AWIDTH_23): EMIF Address[22:0], PB1.10 = A[22] 16 (AWIDTH_24): EMIF Address[23:0], PB1.10 = A[23] |
| MATMD | Match Mode. 0 (PINMATCH): Port Match registers used to provide interrupt / wake sources. 1 (CAPSENSE_TX): Port Match registers used to monitor output pin activity for Capacitive Sensing measurements. 2 (CAPSENSE_RX): Port Match registers used to monitor input pin activity for Capacitive Sensing measurements. 3 (RESERVED): Reserved. |
| EVREGRMD | External Regulator Reset Mode. 0 (RESET_ON_ANY): The pins used by the external regulator will default to digital inputs with weak pull-up enabled on any reset. 1 (RESET_ON_POR): The pins used by the external regulator will default to digital inputs with weak pull-up enabled only on Power-On Reset. Their configured mode will be preserved through all other resets. |
| LOCK | Port Bank Configuration Lock. 0 (UNLOCKED): Port Bank Configuration and Control registers are unlocked. 1 (LOCKED): The following registers are locked from write access: CONTROL1, XBAR0L, XBAR0H, XBAR1, and all PBSKIP registers. |